The present invention relates generally to reducing the leakage power consumption of high performance processors, and more specifically to reducing leakage power consumption by shutting off power to the cache memory.
The need for reducing the power consumption of computers is especially keen for battery-operated systems such as laptops or notebook personal computers. Because the power source of mobile computers accounts for a significant percentage of the bulk and weight of the device, attempts have been made since the advent of laptops to reduce their power consumption. One way of reducing power consumption is to stop the clock input to the processor when the processor is inactive. This method saves significant power since the clock logic is a major power consumer of the processor.
Another area of power consumption that has become more significant recently is leakage power consumption. Leakage power consumption is inherent in semiconductor physics and is a product of the design methods used to create high speed processors. Leakage power consumption is caused by a voltage gradient across a junction within a semiconductor chip that causes current flow. The development of high performance processors has also meant increased leakage power consumption because higher frequency devices employ smaller transistors in larger numbers than ever before. The smaller the transistor channel length and oxide thickness the greater the leakage power consumption.
A significant amount of leakage power consumption could be avoided by cutting the power supply to as much of the CPU as possible when the CPU is not being used. It is desirable, of course, that this power interruption be transparent to the user and comply with design specifications of commercial software developers.